1. Field of the Invention
The invention relates to a circuit for driving a plasma display panel.
2. Description of the Related Art
A plasma display panel has the following advantages in comparison with other displays, and hence, is broadly used in a field of a large-scale outdoor display unit or a large-scale television set.
(a) A plasma display panel can be formed thinner.
(b) A plasma display panel provides a greater display contrast ratio.
(c) A plasma display panel can be readily designed to have a larger screen.
(d) A plasma display panel has a higher response speed.
(e) A plasma display panel emits a light by itself. Hence, it would be possible to emit lights in a plurality of colors through the use of fluorescent materials.
Many plasma display panels have been conventionally suggested, for instance, in Japanese Patent Application Publication No. 5-290742.
FIG. 1 is a perspective view of a conventional plasma display panel 200.
The plasma display panel 200 is designed to include an electrically insulating front substrate 201a and an electrically insulating rear substrate 201b. 
On the front substrate 201a are arranged scanning electrodes 209 and common electrodes 210 spaced away from each other by a certain distance in parallel with each other.
Each of the scanning electrodes 209 and each of the common electrodes 210 are comprised of a bus electrode 203 having electrical conductivity and a principal discharge electrode 202 formed on the bus electrode 203 and used for generating discharge. The principal electrode 202 is composed of transparent material such as ITO (indium tin oxide) in order to prevent reduction in transmissivity.
The scanning electrodes 209 and the common electrodes 210 are covered with a dielectric layer 204a. A protection layer 205 composed of magnesium oxide is formed on the dielectric layer 204a for protecting the dielectric layer 204a from discharge.
On the rear substrate 201b are arranged a plurality of data electrodes 206 in parallel with one another such that the data electrodes 206 extend perpendicularly to the scanning electrode 209 and the common electrode 210.
Cells are arranged at intersections at which, when viewed vertically, the scanning electrode 209 or the common electrode 210 intersects with the data electrode 206.
The data electrodes 206 are covered with a dielectric layer 204b. A plurality of partition walls 207 is formed on the dielectric layer 204b to define discharge spaces. The partition walls 207 extend in parallel with the data electrodes 206.
Phosphor 208 is coated on an exposed surface of the dielectric layer 204b and sidewalls of the partition walls 207. The phosphor 208 converts ultra-violet ray generated in discharge, into a visible light. For instance, red (R), green (G) and blue (B) phosphors are coated in every three cells.
Discharge gas is hermetically introduced into the discharge spaces sandwiched between the front substrate 201a and the rear substrate 201b and partitioned by the partition walls 207.
FIG. 2 is a plan view of a conventional driver circuit 90 for driving the plasma display panel 200.
The plasma display panel 200 has a front surface through which a light passes towards a user, and a rear surface 109a which is a lower surface of the rear substrate 201b. As mentioned below, several circuits are arranged above the rear surface 109a. 
The driver circuit 90 is formed above the rear surface 109a of the plasma display panel 200. The driver circuit 90 is comprised of a common substrate 100, a scanning substrate 101, a relay substrate 111 which mechanically connects the common substrate 100 and the scanning substrate 101 to each other and to which electric charges are collected, data drivers 107, and scanning drivers 108. On the common substrate 100 are formed a sub-scanning block 102 and a sustaining block 103, and on the scanning substrate 101 are formed a priming block 104, a scanning block 105, and a sustaining block 106.
FIG. 3 is a circuit diagram of the driver circuit 90 illustrated in FIG. 2.
The scanning electrode 209 is controlled in operation in accordance with signals transmitted from the scanning drivers 108, and the scanning drivers 108 are controlled in operation by a scanning electrode driving circuit comprised of the priming block 104, the scanning block 105 and the sustaining block 106. The common electrode 210 is controlled in operation by a common electrode driving circuit comprised of the sub-scanning block 102 and the sustaining block 103.
The data electrodes 206 are controlled in operation in accordance with signals transmitted from the data drivers 107.
On the scanning substrate 101 is formed a first circuit for collecting electric charges as well as the scanning electrode driving circuit. On the common substrate 100 is formed a second circuit for collecting electric charges as well as the common electrode driving circuit.
As discharges are generated in the plasma display panel 200, electrical charges are accumulated on the plasma display panel 200. The electric charges accumulated on the plasma display panel 200 are transferred to the relay substrate 111 through the first and second circuits, and collected in capacitors formed on the relay substrate 111.
The conventional driver circuit 90 illustrated in FIGS. 2 and 3 are accompanies with problems as follows.
FIG. 4 is a plan view of the conventional driver circuit 90, showing the first problem of the driver circuit 90.
In the conventional driver circuit 90 illustrated in FIG. 2, since the common substrate 100 and the scanning substrate 101 are formed separately from each other, a heat sink 100a or 101a is also formed in each of the common substrate 100 and the scanning substrate 101. Herein, a heat sink means a part of a switch which generates heat. A principal heat sink is the sustaining blocks 103 and 106.
Since the heat sink 100a formed on the common substrate 100 and the heat skink 101a formed on the scanning substrate 101 generate heat in different amounts, it was not possible to keep switch elements formed on the common and scanning substrates 100 and 101 at the same temperature. As a result, a difference in temperature is generated among switch elements, causing a difference in delay among drive signals.
In addition, since the heat sinks 100a and 101a generate heat at different timing, it was necessary for the conventional driver circuit 90 to include two heat radiator s for the heat sinks 100a and 101a. Such two heat radiator s caused problems of an increase in the number of fabrication steps and an increase in a space necessary for the driver circuit 90 to be formed.
Furthermore, a difference in temperature between the common and scanning substrates 100 and 101 caused variance in CR time constant in accordance with which clamp timing was determined. Thus, clamp timing at which electric charges were collected was inaccurately determined, resulting in that it was not possible to effectively collect electric charges.
FIG. 5 is a plan view of the conventional driver circuit 90, showing the second problem of the driver circuit 90.
In the conventional driver circuit 90, as illustrated in FIG. 5, a sustaining current 110 runs at a ground (GND) line of a module plate. Since the common and scanning substrates 100 and 101 are arranged at opposite ends of the plasma display panel 200, the sustaining current runs in a long path, resulting in generation of high EMI noises.
FIG. 6 is a plan view of the conventional driver circuit 90, showing the third problem of the driver circuit 90.
As mentioned above, the common substrate 100 and the scanning substrate 101 were mechanically connected to each other through the relay substrate 111 in the conventional driver circuit 90. The relay substrate 111 collects electric charges accumulated in charge-collection circuits arranged on the common and scanning substrates 100 and 101. The relay substrate 111 is designed to have an inductance 112 in order to collect electric charges.
However, the inductance 112 causes problems that a wiring length is increased and accordingly a resistance 112a is increased with the result of an increase in a loss of the driver circuit 90.
FIG. 7 is a plan view of the conventional driver circuit 90, showing the fourth problem of the driver circuit 90.
As illustrated in FIG. 7, the common substrate 100 and the scanning substrate 101 include both a Vs clamp circuit 113 and a GND clamp circuit 114. In particular in the common substrate 100, the clamp circuits 113 and 114 make it impossible to locate a waveform-shaping Vs slice diode 115 and a waveform-shaping GND slice diode 116 in the vicinity of an edge of the plasma display panel 200.
FIG. 8A illustrates a desired waveform of a signal output from the driver circuit 90, and FIG. 8B illustrates an actual waveform of a signal output from the driver circuit 90. FIG. 9 is a graph showing a relation between a voltage at which the plasma display panel 200 is driven and the above-mentioned desired and actual waveforms.
As illustrated in FIG. 8B, overshoots occur in the actual waveform due to parasitic inductance of the common substrate 100. This is because the Vs slice diode 115 and the GND slice diode 116 cannot be located in the vicinity of an edge of the plasma display panel 200.
As a result, as illustrated in FIG. 9, a voltage Vw at which a light is wrongly emitted reduces to a degree of the overshoot, and hence, a range Ra of a driving voltage for the actual waveform is reduced in comparison with the same Rd for the desired waveform (driving margin).
Japanese Patent No. 2776419 (Japanese Patent Application Publication No. 9-179521) has suggested a driver circuit for driving a planar display unit including at least one pair of electrodes and panel capacity associated therewith. The driver circuit includes a first path through which a voltage having been applied to the electrodes escapes, a second path through which a voltage is applied to the electrodes, and a capacitor electrically connected to the first and second paths. The first path is comprised of a first coil, a first diode having an anode located close to the electrodes, and a first switch. The second path is comprised of a second coil, a second diode having a cathode located close to the electrodes, and a second switch. The driver circuit further includes a first clamping unit electrically connected between the electrodes and the first coil in the first path, and applying a low voltage to the first path, and a second clamping unit electrically connected between the electrodes and the second coil in the second path, and applying a high voltage to the second path.
Japanese Patent Application Publication No. 11-344952 has suggested a circuit for driving a display unit including a plurality of pairs of control and sustaining electrodes. The circuit includes a sustaining circuit which applies a voltage alternately to the control electrode and the sustaining electrode, and a control circuit. The sustaining circuit is comprised of first and second switching elements electrically connected in series to opposite ends of a capacitor formed between the control and sustaining electrodes, a resonant coil electrically connected in series between the first and second switching elements, and two switching elements electrically connected in series between a power supply line and a ground line. A node to which the two switching elements are electrically connected is electrically connected to a node to which coils of the first and second switching elements are not electrically connected. The control circuit controls the switching elements.
Japanese Patent Application Publication No. 2001-272944 has suggested a circuit for driving a plasma display panel, including a first sustaining driver circuit which controls a voltage of a scanning electrode, and raises a voltage of the sustaining electrode by virtue of a power supply voltage when the scanning electrode is at a voltage of the power supply voltage, a second sustaining driver circuit which controls a voltage of a sustaining electrode, and raises a voltage of the scanning electrode by virtue of a power supply voltage when the sustaining electrode is at a voltage of the power supply voltage, and a relay circuit through which the first and second sustaining driver circuits are electrically connected to each other.